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differential input, 1 msps 10-bit and 12-bit adcs in an 8-lead sot-23 ad7440/ad7450a rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features fast throughput rate: 1 msps specified for v dd of 3 v and 5 v low power at max throughput rate 4 mw max at 1 msps with 3 v supplies 9.25 mw max at 1 msps with 5 v supplies fully differential analog input wide input bandwidth 70 db sinad at 100 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi?/qspi?/microwire?/dsp compatible power-down mode: 1 a max 8-lead sot-23 and msop packages applications transducer interface battery-powered systems data acquisition systems portable instrumentation motor control general description the ad7440/ad7450a 1 are 10-bit and 12-bit high speed, low power, successive approximation (sar) analog-to-digital converters with a fully differential analog input. these parts operate from a single 3 v or 5 v power supply and use advanced design techniques to achieve very low power dissipation at throughput rates up to 1 msps. the sar architecture of these parts ensures that there are no pipeline delays. the parts contain a low noise, wide bandwidth, differential track-and-hold amplifier (t/h) that can handle input frequencies up to 3.5 mhz. the reference voltage is applied externally to the v ref pin and can be varied from 100 mv to 3.5 v depending on the power supply and what suits the application. the value of the reference voltage determines the common-mode voltage range of the part. with this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the device to interface with microprocessors or dsps. the input signals are sampled functional block diagram 03051-a-001 v ref t/h control logic 12-bit successive approximation adc gnd sclk sdata cs v dd ad7440/ad7450a v in+ v in? figure 1. on the falling edge of cs ; the conversion is also initiated at this point. the sar architecture of these parts ensures that there are no pipeline delays. the ad7440 and the ad7450a use ad- vanced design techniques to achieve very low power dissipation at high throughput rates. product highlights 1. operation with either 3 v or 5 v power supplies. 2. high throughput with low power consumption. with a 3 v supply, the ad7440/ad7450a offer 4 mw max power consumption for 1 msps throughput. 3. fully differential analog input. 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. these parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5. variable voltage reference input. 6. no pipeline delay. 7. accurate control of the sampling instant via a cs input and once-off conversion control. 8. enob > eight bits typically with 100 mv reference. 1 protected by u.s. patent number 6,681,332.
ad7440/ad7450a rev. c | page 2 of 28 table of contents ad7440Cspecifications .................................................................... 3 ad7450aCspecifications ................................................................. 5 timing specifications ....................................................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 ter mi nolo g y .................................................................................... 10 ad7440/ad7450aCtypical performance characteristics ....... 12 circuit information ........................................................................ 15 converter operation .................................................................. 15 adc transfer function ............................................................. 15 typical connection diagram ................................................... 16 analog input ............................................................................... 16 driving differential inputs ....................................................... 18 digital inputs .............................................................................. 19 reference ..................................................................................... 19 single-ended operation ............................................................ 20 serial interface ............................................................................ 21 modes of operation ....................................................................... 23 normal mode .............................................................................. 23 power-down mode .................................................................... 23 power-up time .......................................................................... 24 power vs. throughput rate ....................................................... 24 microprocessor and dsp interfacing ...................................... 25 grounding and layout hints .................................................... 26 evaluating the ad7440/ad7450a performance ................... 26 outline dimensions ....................................................................... 27 ordering guide ............................................................................... 28 revision history 9/05rev. b to rev. c changes to ordering guide ............................................................ 28 2/04data sheet changed from rev. a to rev. b added patent note .............................................................................. 1 1/04data sheet changed from rev. 0 to rev. a updated format.................................................................... universal changes to general description ....................................................... 1 changes to table 1 footnotes ............................................................. 3 changes to table 2 footnotes ............................................................. 5 changes to table 3 footnotes ............................................................. 7
ad7440/ad7450a rev. c | page 3 of 28 ad7440Cspecifications table 1. v dd = 2.7 v to 3.6 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.0 v; v dd = 4.75 v to 5.25 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.5 v; v cm 1 = v ref ; t a = t min to t max , unless otherwise noted. temperature range for b version: C40c to +85c. parameter test conditions/comments b version unit dynamic performance f in = 100 khz signal-to-(noise + distortion) (sinad) 2 61 db min total harmonic distortion (thd) 2 C82 db typ C74 db max peak harmonic or spurious noise 2 C82 db typ C76 db max intermodulation distortion (imd) 2 fa = 90 khz, fb = 110 khz second-order terms C83 db typ third-order terms C83 db typ aperture delay 2 5 ns typ aperture jitter 2 50 ps typ full power bandwidth 2 , 3 @ C3 db 20 mhz typ @ C0.1 db 2.5 mhz typ dc accuracy resolution 10 bits integral nonlinearity (inl) 2 0.5 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 10 bits 0.5 lsb max zero-code error 2 2.5 lsb max positive gain error 2 1 lsb max negative gain error 2 1 lsb max analog input full-scale input span 2 v ref 4 v in+ C v inC v absolute input voltage v in+ v cm = v ref v cm v ref /2 v v inC v cm = v ref v cm v ref /2 v dc leakage current 1 a max input capacitance when in track-and-hold 30/10 pf typ reference input v ref input voltage v dd = 4.75 v to 5.25 v (1% tolerance for specified performance) 2.5 5 v v dd = 2.7 v to 3.6 v (1% tolerance for specified performance) 2.0 6 v dc leakage current 1 a max v ref input capacitance when in track-and-hold 10/30 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 a max input capacitance, c in 7 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v; i source = 200 a 2.8 v min v dd = 2.7 v to 3.6 v; i source = 200 a 2.4 v min output low voltage, v ol i sink = 200 a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 7 10 pf max output coding twos complement
ad7440/ad7450a rev. c | page 4 of 28 parameter test conditions/comments b version unit conversion rate conversion time 888 ns with an 18 mhz sclk 16 sclk cycles track-and-hold acquisition time 2 sine wave input 200 ns max step input 290 ns max throughput rate 1 msps max power requirements v dd range: 3 v + 20%/C10%; 5 v 5% 2.7/5.25 v min/v max i dd 8 normal mode (static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.95 ma max v dd = 2.7 v to 3.6 v 1.45 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd = 5 v, 1.55 mw typ for 100 ksps 9 9.25 mw max v dd = 3 v, 0.6 mw typ for 100 ksps 9 4 mw max full power-down mode v dd = 5 v, sclk on or off 5 w max v dd = 3 v, sclk on or off 3 w max 1 common-mode voltage. the input signal can be centered on a dc common-mode voltage in the range specified in figure 28 and figu re 29. 2 see the terminology section. 3 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time can cause t he converter to return an incorrect result. 4 because the input spans of v in+ and v inC are both v ref and are 180 out of phase, the differential voltage is 2 v ref . 5 the ad7440 is functional with a refe rence input from 100 mv and for v dd = 5 v; the reference can range up to 3.5 v. 6 the ad7440 is functional with a refe rence input from 100 mv and for v dd = 3 v; the reference can range up to 2.2 v. 7 guaranteed by characterization. 8 measured with a midscale dc input. 9 see the power vs. throughput section.
ad7440/ad7450a rev. c | page 5 of 28 ad7450aCspecifications table 2. v dd = 2.7 v to 3.6 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.0 v; v dd = 4.75 v to 5.25 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.5 v; v cm 1 = v ref a min max ; t = t to t , unless otherwise noted. temperature range for b version: C40c to +85c. parameter test conditions/comments b version unit dynamic performance f in = 100 khz signal-to-(noise + distortion) (sinad) 2 70 db min total harmonic distortion (thd) 2 v dd = 4.75 v to 5.25 v, C86 db typ C76 db max v dd = 2.7 v to 3.6 v, C84 db typ C74 db max peak harmonic or spurious noise 2 v dd = 4.75 v to 5.25 v, C86 db typ C76 db max v dd = 2.7 v to 3.6 v, C84 db typ C74 db max intermodulation distortion (imd) 2 fa = 90 khz, fb = 110 khz second-order terms C89 db typ third-order terms C89 db typ aperture delay 2 5 ns typ aperture jitter 2 50 ps typ full power bandwidth 2 , 3 @ C3 db 20 mhz typ @ C0.1 db 2.5 mhz typ dc accuracy resolution 12 bits integral nonlinearity (inl) 2 1 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 12 bits 0.95 lsb max zero-code error 2 6 lsb max positive gain error 2 2 lsb max negative gain error 2 2 lsb max analog input full-scale input span 2 v ref 4 v in+ C v inC v absolute input voltage v in+ v cm = v ref v cm v ref /2 v v inC v cm = v ref v cm v ref /2 v dc leakage current 1 a max input capacitance when in track-and-hold 30/10 pf typ reference input v ref input voltage v dd = 4.75 v to 5.25 v (1% tolerance for specified performance) 2.5 5 v v dd = 2.7 v to 3.6 v (1% tolerance for specified performance) 2.0 6 v dc leakage current 1 a max v ref input capacitance when in track-and-hold 10/30 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 a max input capacitance, c in 7 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v; i source = 200 a 2.8 v min v dd = 2.7 v to 3.6 v; i source = 200 a 2.4 v min output low voltage, v ol i sink = 200 a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 7 10 pf max output coding twos complement
ad7440/ad7450a rev. c | page 6 of 28 parameter test conditions/comments b version unit conversion rate conversion time 888 ns with an 18 mhz sclk 16 sclk cycles track-and-hold acquisition time 2 sine wave input 200 ns max step input 290 ns max throughput rate 1 msps max power requirements v dd range: 3 v + 20%/C10%; 5 v 5% 2.7/5.25 v min/v max i dd 8 normal mode (static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.95 ma max v dd = 2.7 v to 3.6 v 1.45 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd = 5 v, 1.55 mw typ for 100 ksps 9 9.25 mw max v dd = 3 v, 0.6 mw typ for 100 ksps 9 4 mw max full power-down v dd = 5 v, sclk on or off 5 w max v dd = 3 v, sclk on or off 3 w max 1 common-mode voltage. the input signal can be centered on a dc common-mode voltage in the range specified in figure 28 and figu re 29. 2 see the terminology section. 3 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time can cause t he converter to return an incorrect result. 4 because the input spans of v in+ and v inC are both v ref and are 180 out of phase, the differential voltage is 2 v ref . 5 the ad7450a is functional with a refe rence input from 100 mv and for v dd = 5 v; the reference can range up to 3.5 v. 6 the ad7450a is functional with a refe rence input from 100 mv and for v dd = 3 v; the reference can range up to 2.2 v. 7 guaranteed by characterization. 8 measured with a midscale dc input. 9 see the power vs. throughput section.
ad7440/ad7450a rev. c | page 7 of 28 timing specifications guaranteed by characterization. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. see figure 2 , figure 3 , and the serial interface section. table 3. v dd = 2.7 v to 3.6 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.0 v; v dd = 4.75 v to 5.25 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.5 v; v cm 1 = v ref ; t a = t min to t max , unless otherwise noted. parameter limit at t min , t max unit description f sclk 2 10 khz min 18 mhz max t convert 16 t sclk t sclk = 1/f sclk 888 ns max t quiet 60 ns min minimum quiet time between the end of a serial read and the next falling edge of cs t 1 10 ns min minimum cs pulse width t 2 10 ns min cs falling edge to sclk falling edge setup time t 3 3 20 ns max delay from cs falling edge until sdata three-state disabled t 4 3 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk ns min sclk low pulse width t 7 10 ns min sclk edge to data valid hold time t 8 4 10 ns min sclk falling edge to sdata three-state enabled 35 ns max sclk falling edge to sdata three-state enabled t power-up 5 1 s max power-up time from full power-down 1 common-mode voltage. 2 mark/space ratio for the sc lk input is 40/60 to 60/40. 3 measured with the load circuit of figure 4 and defined as the time required for the output to cross 0.8 v or 2.4 v with v dd = 5 v or 0.4 v or 2.0 v for v dd = 3 v. 4 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 4. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 25 pf capacitor. this means that the time, t 8 , quoted in the timing specificat ions is the true bus relinquish time of the part and is in dependent of the bus loading. 5 see power-up time section. t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk s dat a 4 leading zeros three-state 12345 13141516 0 0 0 0 db11 db10 db2 db1 db0 b 03051-a-002 figure 2. ad7450a serial interface timing diagram t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk s dat a 4 leading zeros 2 trailing zeros three-state 12345 13141516 0 0 0 0 db9 db8 db0 0 0 b 03051-a-003 figure 3. ad7440 serial interface timing diagram
ad7440/ad7450a rev. c | page 8 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd C0.3 v to +7 v v in+ to gnd C0.3 v to v dd + 0.3 v v inC to gnd C0.3 v to v dd + 0.3 v digital input voltage to gnd C0.3 v to +7 v digital output voltage to gnd C0.3 v to v dd + 0.3 v v ref to gnd C0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial (b version) C40c to +85c storage temperature range C65c to +150c junction temperature 150c ja thermal impedance msop 205.9c/w sot-23 211.5c/w jc thermal impedance msop 43.74c/w sot-23 91.99c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd 1 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 03051-a-004 1.6ma i ol 200 ai oh 1.6v to output pin c l 25pf figure 4. load circuit for digita l output timing specifications 1 transient currents of up to 100 ma do not cause scr latch up. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7440/ad7450a rev. c | page 9 of 28 pin configurations and function descriptions 03051-a-005 v ref v in+ v in? gnd 8 7 6 5 v dd 1 sclk 2 sdata 3 cs 4 ad7440/ ad7450a top view (not to scale) figure 5. pin configuration for 8-lead sot-23 03051-a-006 v dd sclk sdata cs 8 7 6 5 v ref 1 v in+ 2 v in? 3 gnd 4 ad7440/ ad7450a top view (not to scale) figure 6. pin configuration for 8-lead msop table 5. pin function descriptions mnemonic function v ref reference input for the ad7440/ad7450a. an external reference must be applied to this input. for a 5 v power supply, the reference is 2.5 v (1%) for specified performance. for a 3 v power supply, the reference is 2 v (1%) for specified performance. this pin should be decoupled to gnd with a capacitor of at least 0.1 f. see the reference section for more details. v in+ positive terminal for differential analog input. v inC negative terminal for di fferential analog input. gnd analog ground. ground reference point for all circuitry on the ad7440/ad7450a. all analog input signals and any external reference signal should be referred to this gnd voltage. cs chip select. active low logic input. this input provides the dual function of initiating a conversion on the ad7440/ad7450a and framing the seri al data transfer. sdata serial data. logic output. the conversion result from the ad7440/ ad7450a is provided on this o utput as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream of the ad7450a consists of four leading zeros followed by the 12 bits of conversion data, which are provided msb first; the data stream of the ad7440 consists of four leading zeros, followed by the 10 bits of conversion data, follow ed by two trailing zeros. in both cases, the output coding is twos complement. sclk serial clock. logic input. sclk provides the serial clock for a ccessing data from the part. this clock input is also used as th e clock source for the conversion process. v dd power supply input. v dd is 3 v (+20%/C10%) or 5 v (5%). this supply should be decoupled to gnd with a 0.1 f capacitor and a 10 f tantalum capacitor in parallel.
ad7440/ad7450a rev. c | page 10 of 28 terminology signal-to-(noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quanti- zation noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by the following: signal-to-(noise + distortion) = (6.02n + 1.76)db . thus for a 12-bit converter, this is 74 db; and for a 10-bit converter, this is 62 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7440/ad7450a, it is defined as 1 2 6 2 5 2 4 2 3 2 2 v vvvvv thd ++++ = log20)db( where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise peak harmonic (spurious noise) is the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to 0. for example, the second-order terms include (fa + fb) and (fa C fb), while the third- order terms include (2fa + fb), (2fa C fb), (fa + 2fb), and (fa C 2fb). the ad7440/ad7450a is tested using the ccif standard of two input frequencies near the top end of the input bandwidth. in this case, the second-order terms are distanced in frequency from the original sine waves, while the third-order terms are at a frequency close to the input frequencies. as a result, the second- and third- order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in db. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample-to-sample variation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 db or 3 db for a full-scale input. common-mode rejection ratio (cmrr) the common-mode rejection ratio is the ratio of the power in the adc output at full-scale frequency, f , to the power of a 100 mv p-p sine wave applied to the common-mode voltage of v in+ and v inC of frequency f s as follows: cmrr (db) = 10 log ( pf/pfs ) pf is the power at the frequency f in the adc output; pfs is the power at frequency f s in the adc output. integral nonlinearity (inl) this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero-code error this is the deviation of the midscale code transition (111...111 to 000...000) from the ideal v in+ ? v inC (i.e., 0 lsb). positive gain error this is the deviation of the last code transition (011...110 to 011...111) from the ideal v in+ C v inC (i.e., +v ref ? 1 lsb), after the zero code error has been adjusted out. negative gain error this is the deviation of the first code transition (100...000 to 100...001) from the ideal vin+ ? vinC (i.e., Cvref + 1 lsb), after the zero code error has been adjusted out. track-and-hold acquisition time the track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal.
ad7440/ad7450a rev. c | page 11 of 28 power supply rejection ratio (psrr) the power supply rejection ratio is the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency f s . the frequency of this input varies from 1 khz to 1 mhz. psrr (db) = 10log( pf / pf s ) pf is the power at frequency f in the adc output; pfs is the power at frequency f s in the adc output.
ad7440/ad7450a rev. c | page 12 of 28 ad7440/ad7450aCtypical performance characteristics t a = 25c, f s = 1 msps, f sclk = 18 mhz, unless otherwise noted. 75 70 65 60 55 10 100 1000 03051-a-007 frequency (khz) sinad (db) v dd = 5.25v v dd = 4.75v v dd = 3.6v v dd = 2.7v figure 7. ad7450a sinad vs. analog input frequency for various supply voltages 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 1000 100 10000 03051-a-008 frequency (khz) cmrr (db) v dd = 3v v dd = 5v figure 8. cmrr vs. frequency for v dd = 5 v and 3 v 0 ?120 ?20 ?40 ?60 ?80 ?100 0 100 200 300 400 500 600 700 800 900 1000 03051-a-009 supply ripple frequency (khz) psrr (db) 100mv p-p sinewave on v dd no decoupling on v dd v dd = 3v v dd = 5v figure 9. psrr vs. supply ripple fr equency without supply decoupling 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 300 400 500 03051-a-010 frequency (khz) snr (db) 8192 point fft f sample = 1msps f in = 100ksps sinad = +71.7db thd = ?82db sfdr = ?83db figure 10. ad7450a dynamic performance with v dd = 5 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 1024 2048 3072 4096 03051-a-011 code dnl error (lsb) figure 11. typical dnl for the ad7450a for v dd = 5 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 1024 2048 3072 4096 03051-a-012 code inl error (lsb) figure 12. typical inl for the ad7450a for v dd = 5 v
ad7440/ad7450a rev. c | page 13 of 28 3.0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 03051-a-013 v ref (v) change in dnl (lsb) positive dnl negative dnl figure 13. change in dnl vs. v ref for the ad7450a for v dd = 5 v 2.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 2.2 2.5 03051-a-014 v ref (v) change in dnl (lsb) positive dnl negative dnl figure 14. change in dnl vs. v ref for the ad7450a for v dd = 3 v 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 0 0.5 1.0 1.5 2.5 2.0 3.0 3.5 03051-a-015 v ref (v) change in inl (lsb) positive inl negative inl figure 15. change in inl vs. v ref for the ad7450a for v dd = 5 v 2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 2.2 2.5 03051-a-016 v ref (v) change in inl (lsb) positive inl negative inl figure 16. change in inl vs. v ref for the ad7450a for v dd = 3 v 8 0 1 2 3 4 5 6 7 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 03051-a-017 v ref (v) zero-code error (lsb) v dd = 5v v dd = 3v figure 17. change in zero-code error vs. reference voltage for v dd = 5 v and 3 v for the ad7450a 12.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 03051-a-018 v ref (v) effective number of bits v dd = 5v v dd = 3v figure 18. change in enob vs. reference voltage for v dd = 5 v and 3 v for the ad7450a
ad7440/ad7450a rev. c | page 14 of 28 10,000 0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 2044 2045 2046 2047 2048 2049 03051-a-019 code 10,000 codes v in+ = v in? 10,000 conversions f s = 1msps figure 19. histogram of 10,000 conversions of a dc input for the ad7450a with v dd = 5 v 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 300 400 500 03051-a-020 frequency (khz) snr (db) 8192 point fft f sample = 1msps f in = 100khz sinad = +61.6db thd = ?81.7db sfdr = ?83.1db figure 20. ad7440 dynamic performance with v dd = 5 v 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 256 512 768 1024 03051-a-021 code dnl error (lsb) figure 21. typical dnl for the ad7440 for v dd = 5 v 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 256 512 768 1024 03051-a-022 code inl error (lsb) figure 22. typical inl for the ad7440 for v dd = 5 v
ad7440/ad7450a rev. c | page 15 of 28 circuit information the ad7440/ad7450a are 10-bit and 12-bit fast, low power, single-supply, successive approximation analog-to-digital converters (adcs). they can operate with a 5 v or 3 v power supply and are capable of throughput rates up to 1 msps when supplied with an 18 mhz sclk. they require an external reference to be applied to the v ref pin, with the value of the reference chosen depending on the power supply and what suits the application. when they are operated with a 5 v supply, the maximum reference that can be applied is 3.5 v. when they are operated with a 3 v supply, the maximum reference that can be applied is 2.2 v (see the reference section). the ad7440/ad7450a have an on-chip differential track-and- hold amplifier, a successive approximation (sar) adc, and a serial interface housed in either an 8-lead sot-23 or an msop package. the serial clock input accesses data from the part and provides the clock source for the successive approximation adc. the ad7440/ad7450a feature a power-down option for reduced power consumption between conversions. the power- down feature is implemented across the standard serial interface as described in the modes of operation section. converter operation the ad7440/ad7450a are successive approximation adcs based around two capacitive dacs. figure 23 and figure 24 show simplified schematics of the adc in acquisition and conversion phase, respectively. the adc is comprised of control logic, an sar, and two capacitive dacs. in figure 23 (acquisition phase), sw3 is closed, sw1 and sw2 are in position a, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. 03051-a-023 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a figure 23. adc acquisition phase when the adc starts a conversion ( figure 24 ), sw3 opens and sw1 and sw2 move to position b, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and the charge redistri- bution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the compar- ator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adcs output code. the output impedances of the sources driving the v in+ and the v inC pins must be matched; otherwise, the two inputs have different settling times, resulting in errors. 03051-a-024 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a figure 24. adc conversion phase adc transfer function the output coding for the ad7440/ad7450a is twos complement. the designed code transitions occur at successive lsb values (1 lsb, 2 lsbs, and so on). the lsb size of the ad7450a is 2 v ref /4096, and the lsb size of the ad7440 is 2 v ref /1024. the ideal transfer characteristic of the ad7440/ad7450a is shown in figure 25 . 03051-a-025 100...000 analog input (v in+ ? v in? ) 011...111 100...001 100...010 011...110 000...001 111...111 1 lsb 1lsb = 2 v ref /4096 ad7450a 1lsb = 2 v ref /1024 ad7440 +v ref ? 1 lsb ?v ref 0 lsb 000...000 adc code figure 25. ad7440/ad7450a ideal transfer characteristic
ad7440/ad7450a rev. c | page 16 of 28 typical connection diagram figure 26 shows a typical connection diagram for the ad7440/ad7450a for both 5 v and 3 v supplies. in this setup, the gnd pin is connected to the analog ground plane of the system. the v ref pin is connected to either a 2.5 v or a 2 v decoupled reference source, depending on the power supply, to set up the analog input range. the common-mode voltage has to be set up externally and is the value on which the two inputs are centered. the conversion result is output in a 16-bit word with four leading zeros followed by the msb of the 12-bit or 10-bit result. the 10-bit result of the ad7440 is followed by two trailing zeros. for more details on driving the differential inputs and setting up the common mode, refer to the driving differential inputs section. 03051-a-026 ad7440/ ad7450a 0.1 f 0.1 f 10 f v ref v dd v in+ sclk 3v/5v supply serial interface c/ p sdata cs gnd v in? 2v/2.5v v ref *cm is the common-mode voltage. cm* v ref p-p cm* v ref p-p figure 26. typical connection diagram analog input the analog input of the ad7440/ad7450a is fully differential. differential signals have a number of benefits over single- ended signals, including noise immunity based on the devices common-mode rejection, improvements in distortion perfor- mance, doubling of the devices available dynamic range, and flexibility in input ranges and bias points. figure 27 defines the fully differential analog input of the ad7440/ad7450a. 03051-a-027 v ref p-p v in+ v in? v ref p-p ad7440/ ad7450a common-mode voltage figure 27. differential input definitions the amplitude of the differential signal is the difference between the signals applied to the v in+ and v inC pins (i.e., v in+ C v inC ). v in+ and v inC are simultaneously driven by two signals each of amplitude v ref that are 180 out of phase. the amplitude of the differential signal is therefore Cv ref to +v ref peak-to-peak (2 v ref ). this is true regardless of the common mode (cm). the common mode is the average of the two signals, that is, (v in+ + v inC )/2 and is therefore the voltage that the two inputs are centered on. this results in the span of each input being cm v ref /2. this voltage has to be set up externally, and its range varies with v ref . as the value of v ref increases, the common-mode range decreases. when driving the inputs with an amplifier, the actual common-mode range is determined by the amplifiers output voltage swing. figure 28 and figure 29 show how the common-mode range typically varies with v ref for both a 5 v and a 3 v power supply. the common mode must be in this range to guarantee the functionality of the ad7440/ad7450a. for ease of use, the common mode can be set up to equal v ref , resulting in the differential signal being v ref centered on v ref . when a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude Cv ref to +v ref , corresponding to the digital codes of 0 to 4096 in the case of the ad7450a and 0 to 1024 in the ad7440. 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 03051-a-028 v ref (v) common-mode voltage (v) 1.75v 3.25v common-mode range figure 28. input common-mode range vs. v ref (v dd = 5 v and v ref (max) = 3.5 v) 2.5 0.5 1.0 1.5 2.0 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 03051-a-029 v ref (v) common-mode voltage (v) 1v 2v common-mode range figure 29. input common-mode range vs. v ref (v dd = 3 v and v ref (max) =2v)
ad7440/ad7450a rev. c | page 17 of 28 figure 30 shows examples of the inputs to v in+ and v inC for different values of v ref for v dd = 5 v. it also gives the maximum and minimum common-mode voltages for each reference value according to figure 28 . 03051-a-030 common-mode (cm) cm min = 1v cm max = 4v reference = 2v v in? v in+ 2v p-p common-mode (cm) cm min = 1.25v cm max = 3.75v reference = 2.5v v in? v in+ 2.5v p-p figure 30. examples of the analog inputs to v in+ and v inC for different values of v ref for v dd = 5 v analog input structure figure 31 shows the equivalent circuit of the analog input structure of the ad7440/ad7450a. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this causes these diodes to become forward biased and start conducting into the substrate. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the capacitors, c1 in figure 31 , are typically 4 pf and can primarily be attributed to pin capacitance. the resistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 100 . the capacitors, c2, are the adcs sampling capacitors and have a capacitance of 16 pf typically. 03051-a-031 c1 c2 r1 d d c1 c2 r1 d d v dd v dd v in+ v in? figure 31. equivalent analog input circuit conversion phaseCswitches open ; track phaseCswitches closed for ac applications, removing high frequency components from the analog input signal through the use of an rc low-pass filter on the relevant analog input pins is recommended. in applica- tions where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impe- dance source. large source impedances significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of op amp is a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases, and performance degrades. figure 32 shows a graph of thd vs. the analog input signal frequency for different source impedances for v dd = 5 v. 0 ?100 ?80 ?60 ?40 ?20 10 100 1000 03051-a-032 input frequency (khz) thd (db) t a = 25 c v dd = 5v r in = 1k r in = 510 r in = 10 r in = 300 figure 32. thd vs. analog input frequency for various source impedances for v dd = 5 v figure 33 shows a graph of the thd vs. the analog input frequency for v dd of 5 v 5% and 3 v + 20%/C10%, while sampling at 1 msps with an sclk of 18 mhz. in this case, the source impedance is 10 . ?50 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 10 100 1000 03051-a-033 input frequency (khz) thd (db) t a = 25 c v dd = 2.7v v dd = 3.6v v dd = 5.25v v dd = 4.75v figure 33. thd vs. analog input frequency for 3 v and 5 v supply voltages
ad7440/ad7450a rev. c | page 18 of 28 driving differential inputs differential operation requires v in+ and v inC to be driven simultaneously with two equal signals that are 180 out of phase. the common mode must be set up externally and has a range determined by v ref , the power supply, and the particular amplifier used to drive the analog inputs (see figure 28 and figure 29 ). differential modes of operation with either an ac or dc input provide the best thd performance over a wide frequency range. because not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-differential conversion. differential amplifier an ideal method of applying differential drive to the ad7440/ad7450a is to use a differential amplifier such as the ad8138. this part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. in both cases, the analog input needs to be bipolar. it also provides common-mode level shifting and buffering of the bipolar input signal. figure 34 shows how the ad8138 can be used as a single-ended-to-differential amplifier. the positive and negative outputs of the ad8138 are connected to the respective inputs on the adc via a pair of series resistors to minimize the effects of switched capacitance on the front end of the adcs. the rc low-pass filter on each analog input is recommended in ac applications to remove high frequency components of the analog input. the architecture of the ad8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. if the analog input source being used has zero impedance, all four resistors (r g 1, r g 2, r f 1, and r f 2) should be the same. if the source has a 50 impedance and a 50 termination, for example, the value of r g 2 should be increased by 25 to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see figure 34 ). the outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude and are exactly 180 out of phase. the ad8138 is specified with +3 v, +5 v, and 5 v power supplies, but the best results are obtained with a 5 v supply. the ad8132 is a lower cost device that could also be used in this configuration with slight differences in characteristics to the ad8138 but with similar performance and operation. 03051-a-034 +2.5v gnd ?2.5v ad8138 51 r g 1 r s * c* c* r s * r g 2 r f 2 v ocm r f 1 3.75v v in+ v in? v ref 2.5v 1.25v 3.75v 2.5v 1.25v ad7440/ ad7450a *mount as close to the ad7440/ad7450a as possible and ensure high precision r s and c s are used. r s ?50 ; c?1nf r g 1 = r f 1 = r f 2 = 499 ; r g 2 = 523 external v ref (2.5v) figure 34. using the ad8138 as a single-ended-to-differential amplifier
ad7440/ad7450a rev. c | page 19 of 28 op amp pair an op amp pair can be used to directly couple a differential signal to the ad7440/ad7450a. the circuit configurations shown in figure 35 and figure 36 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. the voltage applied to point a sets up the common-mode voltage. in both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. the ad8022 is a suitable dual op amp that could be used in this configuration to provide differential drive to the ad7440/ad7450a. take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. the driver circuits in figure 35 and figure 36 are optimized for dc coupling applications requiring best distortion performance. the circuit configuration shown in figure 35 converts a unipolar, single-ended signal into a differential signal. the differential op amp driver circuit in figure 36 is configured to convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the v ref level of the adc. 03051-a-036 v dd 2 v ref p-p v ref gnd 390 220 220 220 10k 27 27 0.1 f v+ v? v+ v? a v in+ v in? v ref ad7440/ ad7450a external v ref figure 35. dual op amp circuit to convert a single-ended unipolar signal into a differential signal 03051-a-035 gnd v+ v? v+ v? a v in+ v dd v in? v ref ad7440/ ad7450a 2 v ref p-p 390 220 220 220 220 10k 20k 27 27 0.1 f external v ref figure 36. dual op amp circuit to convert a single-ended bipolar signal into a differential signal rf transformer an rf transformer with a center tap offers a good solution for generating differential inputs in systems that do not need to be dc-coupled. figure 37 shows how a transformer is used for single-ended-to-differential conversion. it provides the benefits of operating the adc in the differential mode without contri- buting additional noise and distortion. an rf transformer also has the benefit of providing electrical isolation between the signal source and the adc. a transformer can be used for most ac applications. the center tap is used to shift the differential signal to the common-mode level required; in this case, it is connected to the reference so the common-mode level is the value of the reference. 03051-a-037 r r c 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v r v in+ v in? v ref ad7440/ ad7450a external v ref figure 37. using an rf transforme r to generate di fferential inputs digital inputs the digital inputs applied to the device are not limited by the maximum ratings, which limit the analog limits. instead the digital inputs applied, cs and sclk, can go to 7 v and are not restricted by the v dd + 0.3 v limits as on the analog input. the main advantage of the inputs not being restricted to the v dd + 0.3 v limit is that power supply sequencing issues are avoided. if cs and sclk are applied before v dd , there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 v was applied prior to v dd . reference an external reference source is required to supply the reference to the device. this reference input can range from 100 mv to 3.5 v. with a 5 v power supply, the specified reference is 2.5 v and the maximum reference is 3.5 v. with a 3 v power supply, the specified reference is 2 v and the maximum reference is 2.2 v. in both cases, the reference is functional from 100 mv. ensure that, when choosing the reference value for a particular application, the maximum analog input range (v in max) is never greater than v dd + 0.3 v to comply with the maximum ratings of the device. the following two examples calculate the maximum v ref input that can be used when operating the ad7440/ad7450a at a v dd of 5 v and 3 v, respectively.
ad7440/ad7450a rev. c | page 20 of 28 example 1 table 6. examples of suitable voltage references output voltage (v) initial accuracy (%) operating current (a) v in max v dd 0.3 v in max v ref v ref /2 reference ad780 2.5/3 0.04 1000 if v dd = 5 v, then v in max = 5.3 v. therefore 3 v ref /2 = 5.3 v v ref max = 3.5 v thus, when operating at v dd = 5 v, the value of v ref can range from 100 mv to a maximum value of 3.5 v. when v dd = 4.75 v, v ref max = 3.17 v. example 2 i max dd 03 i max ref ref /2 if dd 3 ten i max 33 terefore 3 ref /2 33 ref max 22 tus en operating at dd 3 te alue of ref can range from 100 m to a maximum alue of 22 en dd 27 ref max 2 tese examples so tat te maximum reference applie to te ad7440/ad7450a is irectl epenent on te alue applie to dd te alue of te reference sets te analog input span an te common-moe oltage range errors in te reference source result in gain errors in te ad7440/ad7450a transfer function an a to specifie full-scale errors on te part a 01 f capacitor soul e use to ecouple te ref pin to d figure 3 sos a tpical connection iagram for te ref pin tale 6 lists examples of suitale oltage references 03051-a-038 1 ad780 nc 8 2 v in nc 7 3 gnd 6 4 temp 5 opsel trim v out ad7440/ ad7450a* v ref 2.5v nc v dd nc v dd nc = no connect 10nf 0.1 f 0.1 f 0.1 f *additional pins omitted for clarity figure 38. typical v ref connection diagram for v dd = 5 v adr421 2.5 0.04 500 adr420 2.048 0.05 500 single-ended operation when supplied with a 5 v power supply, the ad7440/ad7450a can handle a single-ended input. the design of these devices is optimized for differential operation, so with a single-ended input, performance degrades. linearity degrades by typically 0.2 lsb, the full-scale errors degrade typically by 1 lsb, and ac performance is not guaranteed. to operate the ad7440/ad7450a in single-ended mode, the v input is coupled to the signal source, while the v in inC input is biased to the appropriate voltage corresponding to the midscale code transition. this voltage is the common mode, which is a fixed dc voltage (usually the reference). the v in input swings around this value and should have a voltage span of 2 v ref to make use of the full dynamic range of the part. the input signal therefore has peak-to-peak values of common mode v ref . if the analog input is unipolar, an op amp in a noninverting unity gain configuration can be used to drive the v in pin. the adc operates from a single supply, so it is necessary to level shift ground-based bipolar signals to comply with the input requirements. an op amp can be configured to rescale and level shift the ground-based bipolar signal, so it is compatible with the selected input range of the ad7440/ad7450a ( figure 39 ). 03051-a-039 r 5v 2.5v 0v +2.5v 0v ?2.5v r r 0.1 f r ad7440/ ad7450a v ref v in+ v in? v in external v ref (2.5v) figure 39. applying a bipolar single -ended input to the ad7440/ad7450a
ad7440/ad7450a rev. c | page 21 of 28 sixteen serial clock cycles are required to perform a conversion and access data from the ad7440/ad7450a. serial interface cs going low provides the first leading zero to be read in by the dsp or microcontroller. the remaining data is then clocked out on the subsequent sclk falling edges beginning with the second leading zero. thus, the first falling clock edge on the serial clock provides the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that before the next conversion is initiated, enough time is left to meet the acquisition and quiet time specifications (see timing examples 1 and 2). to achieve 1 msps with an 18 mhz clock for v figure 2 and figure 3 show detailed timing diagrams for the serial interface of the ad7450a and the ad7440, respectively. the serial clock provides the conversion clock and also controls the transfer of data from the devices during conversion. cs initiates the conversion process and frames the data transfer. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state. the analog input is sampled and the conversion is initiated at this point. the conversion requires 16 sclk cycles to complete. once 13 sclk falling edges have occurred, the track-and-hold goes back into track on the next sclk rising edge, as shown at point b in dd = 3 v and 5 v, an 18-clock burst performs the conversion and leaves enough time before the next conversion for the acquisition and quiet time. figure 2 and figure 3 . on the 16th sclk falling edge, the sdata line goes back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion terminates and the sdata line goes back into three-state. in applications with a slower sclk, it may be possible to read in data on each sclk rising edge; th at is, the first rising edge of sclk after the the conversion result from the ad7440/ad7450a is provided on the sdata output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream of the ad7450a consists of four leading zeros followed by 12 bits of conversion data provided msb first; the data stream of the ad7440 consists of four leading zeros, followed by the 10 bits of conversion data followed by two trailing zeros, which is also provided msb first. in both cases, the output coding is twos complement. cs falling edge would have the leading zero provided and the 15th sclk edge would have db0 provided. 03051-a-040 t 2 t 8 t 6 t 5 t convert cs sclk 12345 13141516 12.5(1/f sclk ) t acquisition 1/throughput t quiet 10ns b c figure 40. serial interface timing example
ad7440/ad7450a rev. c | page 22 of 28 timing example 1 having f sclk = 18 mhz and a throughput rate of 1 msps gives a cycle time of 1/ throughput = 1/1,000,000 = 1 s a cycle consists of t 2 + 12.5(1/ f sclk ) + t acq = 1 s therefore, if t 2 = 10 ns 10 ns + 12.5(1/18 mhz) + t acq = 1 s t acq = 296 ns this 296 ns satisfies the requirement of 290 ns for t acq . from figure 40 , t acq comprises 2.5(1/ f sclk ) + t 8 + t quiet where t 8 = 35 ns. this allows a value of 122 ns for t quiet , satisfying the minimum requirement of 60 ns. timing example 2 having f sclk = 5 mhz and a throughput rate of 315 ksps gives a cycle time of 1/ throughput = 1/315,000 = 3.174 s a cycle consists of t 2 + 12.5(1/ f sclk ) + t acq = 3.174 s therefore, if t 2 is 10 ns 10 ns + 12.5(1/5 mhz) + t acq = 3.174 s t acq = 664 ns this 664 ns satisfies the requirement of 290 ns for t acq . from figure 40 , t acq comprises 2.5(1/ f sclk ) + t 8 + t quiet where t 8 = 35 ns. this allows a value of 129 ns for t quiet , satisfying the minimum requirement of 60 ns. as in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 60 ns minimum t quiet between conversions. in timing example 2, the signal should be fully acquired at approximately point c in figure 40 .
ad7440/ad7450a rev. c | page 23 of 28 modes of operation power-down mode the operational mode of the ad7440/ad7450a is selected by controlling the logic state of the cs signal during a conversion. there are two possible modes of operation, normal and power- down. the point at which this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the adc is then powered down for a relatively long duration between these bursts of conversions. when the ad7440/ad7450a are in the power-down mode, all analog circuitry is powered down. to enter power-down mode, the conversion process must be interrupted by bringing cs is pulled high after the conversion has been initiated determines whether or not the device enters power-down mode. similarly, if already in power-down, cs controls whether the devices return to normal operation or remain in power-down. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. cs high anywhere after the second falling edge of sclk and before the 10th falling edge of sclk, as shown in figure 42 . normal mode this mode is intended for fastest throughput rate performance. the user does not have to worry about any power-up times with the ad7440/ad7450a remaining fully powered up all the time. 03051-a-042 1 10 sclk s dat a three-state 2 cs figure 41 shows the general diagram of the operation of the ad7440/ad7450a in this mode. the conversion is initiated on the falling edge of cs , as described in the serial interface section. to ensure the part remains fully powered up, figure 42. entering power-down mode cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs once has been brought high in this window of sclks, the part enters power-down, the conversion that was initiated by the falling edge of cs . cs is terminated, and sdata goes back into three-state. the time from the rising edge of cs to sdata three-state enabled is never greater than t 03051-a-041 11 0 cs sclk sdata 16 4 leading zeros + conversion result 8 (refer to the timing specifications). if cs is brought high before the second sclk falling edge, the part remains in normal mode and does not power down. this avoids accidental power-down due to glitches on the cs line. figure 41. normal mode operation if cs in order to exit this mode of operation and power up the ad7440/ad7450a again, a dummy conversion is performed. on the falling edge of is brought high any time after the 10th sclk falling edge, but before the 16th sclk falling edge, the part remains powered up but the conversion terminates and sdata goes back into three-state. sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. cs , the device begins to power up and continues to power up as long as cs is held low until after the falling edge of the 10th sclk. the device is fully powered up after 1 s has elapsed and, as shown in cs figure 43 , valid data results from the next conversion. may idle high until the next conversion or may idle low until sometime prior to the next conversion. once a data transfer is complete, when sdata has returned to three-state, another conversion can be initiated after the quiet time, t quiet , has elapsed by again bringing cs low. 03153-a-031 cs sclk sdata 1 10 16 1 10 16 a this part is fully powered up with v in fully acquired part begins to power up invalid data valid data t power-up figure 43. exiting power-down mode
ad7440/ad7450a rev. c | page 24 of 28 if cs is brought high before the 10th falling edge of sclk, the ad7440/ad7450a again goes back into power-down. this avoids accidental power-up due to glitches on the cs line or an inadvertent burst of eight sclk cycles while cs is low. so although the device may begin to power up on the falling edge of cs , it again powers down on the rising edge of cs as long as it occurs before the 10th sclk falling edge. power-up time the power-up time of the ad7440/ad7450a is typically 1 s, which means that with any frequency of sclk up to 18 mhz, one dummy cycle is always sufficient to allow the device to power up. once the dummy cycle is complete, the adc is fully powered up and the input signal is acquired properly. the quiet time, t quiet , must still be allowed from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of cs . when running at the maximum throughput rate of 1 msps, the ad7440/ad7450a power up and acquire a signal within 0.5 lsb in one dummy cycle, 1 s. when powering up from the power-down mode with a dummy cycle, as in figure 43 , the track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 43 . although at any sclk frequency one dummy cycle is sufficient to power up the device and acquire v in , it does not mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; 1 s is sufficient to power up the device and acquire the input signal. for example, if a 5 mhz sclk frequency was applied to the adc, the cycle time would be 3.2 s (1/(5 mhz) 16). in one dummy cycle, 3.2 s, the part would be powered up and v in acquired fully. however, after 1 s with a 5 mhz sclk, only five sclk cycles would have elapsed. at this stage, the adc would be fully powered up and the signal acquired. so in this case, the cs can be brought high after the 10th sclk falling edge and brought low again after a time, t quiet , to initiate the conversion. when power supplies are first applied to the device, the adc may power up in either power-down mode or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. likewise, if the user wants the part to power up in power-down mode, the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as the one shown in figure 42 . once supplies are applied to the ad7440/ad7450a, the power- up time is the same as that when powering up from power- down mode. it takes about 1 s to power up fully if the part powers up in normal mode. it is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed directly after the dummy conversion, ensure that adequate acquisition time has been allowed. as mentioned earlier, when powering up from the power-down mode, the part returns to track mode upon the first sclk edge applied after the falling edge of cs . however, when the adc powers up initially after supplies are applied, the track-and-hold is already in track mode. assuming the user has the facility to monitor the adc supply current, this means the adc powers up in the desired mode of operation, and thus a dummy cycle is not required to change mode. a dummy cycle is therefore not required to place the track-and-hold into track mode. power vs. throughput rate by using the power-down mode on the ad7440/ad7450a when not converting, the average power consumption of the adc decreases at lower throughput rates. figure 44 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption is reduced accordingly for both 5 v and 3 v power supplies. for example, if the ad7440/ad7450a are operated in continuous sampling mode with a throughput rate of 100 ksps and an sclk of 18 mhz, and the device is placed in power- down mode between conversions, the power consumption is calculated as follows: power dissipation during normal operation = 9.25 mw max (for v dd = 5 v) if the power-up time is one dummy cycle (1 s), and the remaining conversion time is another cycle (1 s), the ad7440/ad7450a can be said to dissipate 9.25 mw for 2 s 1 during each conversion cycle. if the throughput rate = 100 ksps, the cycle time = 10 s and the average power dissipated during each cycle is (2/10) 9.25 mw = 1.85 mw . for the same scenario, if v dd = 3 v, the power dissipation during normal operation is 4 mw max. the ad7440/ad7450a can now be said to dissipate 4 mw for 2 s 1 during each conversion cycle. 1 this figure assumes a very short time to enter power- down mode. this increases as the burst of clocks used to enter this mode is increased.
ad7440/ad7450a rev. c | page 25 of 28 thus, the average power dissipated during each cycle with a throughput rate of 100 ksps is (2/10) 4 mw = 0.8 mw. the connection diagram is shown in figure 45 . the adsp-21xx has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronization signal generated on the tfs is tied to this is how the power numbers in figure 44 are calculated. for throughput rates above 320 ksps, it is recommended to reduce the serial clock frequency for best power performance. cs and, as with all signal processing applications, equidistant sampling is necessary. however in this example, the timer interrupt is used to control the sampling rate of the adc; under certain conditions, equidistant sampling may not be achieved. 03051-a-044 throughput (ksps) 100 0 350 power (mw) 0.01 50 100 150 200 250 300 0.1 1 10 v dd = 5v v dd = 3v the timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and therefore the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given (ax0 = tx0), the state of the sclk is checked. the dsp waits until the sclk has gone high, low, and high again before starting transmission. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, then the data may be transmitted or it may wait until the next clock edge. figure 44. power vs. throughp ut rate for power-down mode microprocessor and dsp interfacing 03051-a-045 ad7440/ ad7450a* adsp-21xx* sclk dr rfs tfs sclk sdata cs *additional pins removed for clarity the serial interface on the ad7440/ad7450a allows the parts to be directly connected to many different microprocessors. this section explains how to interface the ad7440/ad7450a with some of the more common microcontroller and dsp serial interface protocols. ad7440/ad7450a to adsp-21xx the adsp-21xx family of dsps is interfaced directly to the ad7440/ad7450a without any glue logic required. figure 45. interfacing to the adsp-21xx the sport control register should be set up as follows: for example, the adsp-2111 has a master clock frequency of 16 mhz. if the sclkdiv register is loaded with the value 3, an sclk of 2 mhz is obtained and eight master clock periods elapse for every sclk period. if the timer registers are loaded with the value 803, then 100.5 sclks occur between interrupts and subsequently between transmit instructions. this situation results in nonequidistant sampling as the transmit instruction is occurring on a sclk edge. if the number of sclks between interrupts is a whole integer figure of n, equidistant sampling is implemented by the dsp. table 7. parameter description tfsw = rfsw = 1 alternate framing invrfs = invtfs = 1 active low frame signal dtype = 00 right-justify data slen = 1111 16-bit data-words isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word irfs = 0 itfs = 1 to implement power-down mode, slen should be set to 1001 to issue an 8-bit sclk burst.
ad7440/ad7450a rev. c | page 26 of 28 ad7440/ad7450a to tms320c5x/c54x grounding and layout hints the serial interface on the tms320c5x/c54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7440/ad7450a. the the printed circuit board that houses the ad7440/ad7450a should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place, a star ground point established as close to the gnd pin on the ad7440/ad7450a as possible. avoid running digital lines under the devices because this couples noise onto the die. the analog ground plane should be allowed to run under the ad7440/ad7450a to avoid noise coupling. the power supply lines to the ad7440/ad7450a should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. cs input allows easy interfacing between the tms320c5x/c54x and the ad7440/ad7450a without any glue logic required. the serial port of the tms320c5x/c54x is set up to operate in burst mode with internal clkx (tx serial clock) and fsx (tx frame sync). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1, and txm = 1. the format bit, fo, may be set to 1 to set the word length to eight bits to implement the power-down mode on the ad7440/ad7450a. the con- nection diagram is shown in figure 46 . for signal processing applications, it is imperative that the frame synchronization signal from the tms320c5x/c54x provide equidistant sampling. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. ad7440/ ad7450a* tms320c5x/ c54x* clkx dr fsx fsr sclk sdata cs clkr 03051-a-046 *additional pins removed for clarity in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. figure 46. interfacing to the tms320c5x/c54 ad7440/ad7450a to dsp56xxx the connection diagram in figure 47 shows how the device can be connected to the synchronous serial interface (ssi) of the dsp56xxx family of dsps from motorola. the ssi is operated in synchronous mode (syn bit in crb = 1) with internally generated 1-word frame sync for both tx and rx (bits fsl1 = 0 and fsl0 = 0 in crb). set the word length to 16 by setting bits wl1 = 1 and wl0 = 0 in cra. to implement power-down mode on the ad7440/ad7450a, the word length can be changed to 8 bits by setting bits wl1 = 0 and wl0 = 0 in cra. for signal processing applications, it is imperative that the frame synchronization signal from the dsp56xxx provide equidistant sampling. evaluating the ad7440/ad7450a performance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7440/ad7450a evaluation board, as well as many other analog devices evaluation boards ending with the cb designator, to demonstrate and evaluate the ac and dc performance of the ad7440/ad7450a. ad7440/ ad7450a* 03051-a-047 dsp56xxx* sclk srd sr2 sclk sdata cs *additional pins removed for clarity the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the device. see the ad7440/ad7450a application note that accompanies the evaluation kit for more information. figure 47. interfacing to the dsp56xxx
ad7440/ad7450a rev. c | page 27 of 28 outline dimensions 13 56 2 8 4 7 2.90 bsc 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.22 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc pin 1 indicator compliant to jedec standards mo-178-ba figure 48. 8-lead small outline transistor package [sot-23] (rt-8) dimensions shown in millimeters compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 49. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ad7440/ad7450a rev. c | page 28 of 28 ordering guide model temperature range linearity error (lsb) 1 package description package option branding AD7440BRT-reel7 C40c to +85c 0.5 8-lead sot-23 rt-8 ctb AD7440BRT-r2 C40c to +85c 0.5 8-lead sot-23 rt-8 ctb AD7440BRTz-reel7 2 C40c to +85c 0.5 8-lead sot-23 rt-8 c3j AD7440BRTz-r2 2 C40c to +85c 0.5 8-lead sot-23 rt-8 c3j ad7440brm C40c to +85c 0.5 8-lead msop rm-8 ctb ad7440brm-reel7 C40c to +85c 0.5 8-lead msop rm-8 ctb ad7440brmz 2 C40c to +85c 0.5 8-lead msop rm-8 c3j ad7450abrt-reel7 C40c to +85c 1 8-lead sot-23 rt-8 csb ad7450abrt-r2 C40c to +85c 1 8-lead sot-23 rt-8 csb ad7450abrtz-reel7 2 C40c to +85c 1 8-lead sot-23 rt-8 c4n ad7450abrm C40c to +85c 1 8-lead msop rm-8 csb ad7450abrm-reel7 C40c to +85c 1 8-lead msop rm-8 csb ad7450abrmz 2 C40c to +85c 1 8-lead msop rm-8 c4n eval-ad7440cb 3 evaluation board eval-ad7450acb 3 evaluation board eval-control brd2 4 controller board 1 linearity error here refers to integral nonlinearity error. 2 z = pb-free part. 3 this can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demons tration purposes. 4 evaluation board controller. this board is a complete unit allo wing a pc to control and communicate with all analog devices e valuation boards en ding in the cb designator. for a complete evalua tion kit, order the adc evalua tion board (that is, the eval-a d7450acb or eval-ad7440cb), the e val-control brd2, and a 12 v ac transformer. see the ad7440/ad7450a applic ation note that accompan ies the evaluation kit for more information. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c03051C0C9/05(c)

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